Mips r3000 instruction set

MIPS R3000[2] from publication: Software Solutions for Single Instruction Moreover, the multiplication and division latencies were set to 5 and 35MIPS-1 is the ISA found in the R2000 and R3000 generation CPUs. It is a 32-bit ISA, and defines the basic instruction set. Any application written. In MIPS, data must be in registers to perform arithmetic. Register $1 is reserved for the assembler to handle pseudo instructions and large constants.